This application claims a priority based on Japanese Patent Application No. 2000-59348 filed on Mar. 3, 2000, the entire contents of which are incorporated herein by reference for all purposes.
1. Field of the Invention
The present invention relates to an entertainment apparatus for carrying out video games and the like, particularly, to a method for controlling a bus inside the entertainment apparatus.
2. Description of the Related Art
Conventionally, an entertainment apparatus for carrying out video games and the like has been known. Some of peripheral devices such as a DVD, used for recent entertainment apparatuses require a higher transfer rate. In order to employ such device, the transfer rate should be increased between, for example, a CPU and the peripheral device.
The width of the data bus could be widened to raise the transfer rate, but simple widening of the width of the data bus necessitates increase of the number of pins of a package of a CPU and the like, thus results in increase of the cost. Another idea to reduce the number of pins is the multiplexed bus like PCT. However, most of conventional peripheral devices require independent address and data lines
An object of the present invention is to increase the transfer rate without increasing the number of pins of a package of a device such as a CPU.
An entertainment apparatus according to the present invention comprises a peripheral device and a controller for controlling the peripheral device (for example, a CPU or an input/output sub-processor). In such entertainment apparatus, the peripheral device and the controller are connected each other by an address bus and a data, and at least a part of the address bus is used as the data bus in a specific data transfer.
In the entertainment apparatus, the specific data transfer may be performed, for example, during the assertion of the DMA(Direct Memory Access) acknowledge signal.
Further, the peripheral device may be a PC card interface portion, and in accordance with a type of a PC card connected thereto, it is determined whether at least a part of the address bus is used as the data bus.